The present invention is directed to methods for implementing function tables in integrated circuit designs. More specifically, but without limitation thereto, the present invention is directed to implementing a function table with random logic elements.
Designs often contain function tables, that is, tables of systems of Boolean operators, or functions, that are typically implemented in read-only memory (ROM). Examples of such tables may be found in U.S. patent application Ser. No. 09/679,209 by Andreev, et. al for “FAST FLEXIBLE SEARCH ENGINE FOR LONGEST PREFIX MATCH” filed on Oct. 4, 2000, and U.S. patent application Ser. No. 09/679,313 by Andreev, et al. for “FLEXIBLE SEARCH ENGINE HAVING SORTED BINARY SEARCH TREE FOR PERFECT MATCH”, filed on Oct. 4, 2000. For small tables that have from about 30 to 1,000 entries, implementing function tables in ROM becomes expensive. This is because ROM compilers create overhead such decoders and I/O pins that are independent of the number of words and bits. This overhead is relatively small for tables having more than 16,000 entries, but becomes extremely large for small tables. Another disadvantage in using ROM for small tables is that the floorplan and design flow of an integrated circuit are complicated by the use of ROM, since ROM megacells are typically placed manually, creating blockages for placement and routing of random logic cells.